BCM5722 Programmer’s Guide
10/15/07
Data Link Status Register (Offset 0x7D04) .........................................................................................397
Data Link Attention Register (Offset 0x7D08) .....................................................................................398
Data Link Attention Mask Register (Offset 0x7D0C) ...........................................................................398
Next Transmit Sequence Number Debug Register (Offset 0x7D10)...................................................399
ACKed Transmit Sequence Number Debug Register (Offset 0x7D14)...............................................399
Purged Transmit Sequence Number Debug Register (Offset 0x7D18)...............................................399
Receive Sequence Number Debug Register (Offset 0x7D1C)............................................................399
Data Link Replay Register (Offset 0x7D20) ........................................................................................399
Data Link ACK Timeout Register (Offset 0x7D24) ..............................................................................400
Power Management Threshold Register (Offset 0x7D28)...................................................................400
Retry Buffer Write Pointer Debug Register (Offset 0x7D2C)...............................................................400
Retry Buffer Read Pointer Debug Register (Offset 0x7D30)...............................................................400
Retry Buffer Purged Pointer Debug Register (Offset 0x7D34)............................................................401
Retry Buffer Read/Write Debug Port (Offset 0x7D38).........................................................................401
Error Count Threshold Register (Offset 0x7D3C)................................................................................401
TLP Error Counter Register (Offset 0x7D40) ......................................................................................401
DLLP Error Counter (Offset 0x7D44) ..................................................................................................402
NAK Received Counter (Offset 0x7D48).............................................................................................402
Data Link Test Register (Offset 0x7D4C)............................................................................................402
Packet BIST Register (Offset 0x7D50)................................................................................................403
Link PCIe 1.1 Control Register (0x7D54) ............................................................................................404
PHY Mode Register (Offset 0x7E00)...................................................................................................405
PHY/Link Status Register (Offset 0x7E04)..........................................................................................405
PHY/Link LTSSM Control Register (Offset 0x7E08) ...........................................................................406
PHY/Link Training Link Number (Offset 0x7E0C) ...............................................................................406
PHY/Link Training Lane Number (Offset 0x7E10)...............................................................................406
PHY/Link Training N_FTS (Offset 0x7E14).........................................................................................407
PHY Attention Register (Offset 0x7E18) .............................................................................................407
PHY Attention Mask Register (Offset 0x7E1C)...................................................................................408
PHY Receive Error Counter (Offset 0x7E20) ......................................................................................408
PHY Receive Framing Error Counter (Offset 0x7E24)........................................................................408
PHY Receive Error Threshold Register (Offset 0x7E28).....................................................................409
PHY Test Control Register (Offset 0x7E2C) .......................................................................................409
PHY/SerDes Control Override Register (Offset 0x7E30)....................................................................411
PHY Timing Parameter Override Register (Offset 0x7E34) ................................................................412
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