Broadcom BCM5722 - Page 42

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page xlii Document 5722-PG101-R
Table 75: Required Memory Regions for WOL Pattern ..................................................................................160
Table 76: 10/100 Mbps Mode Frame Patterns Memory .................................................................................163
Table 77: Frame Control Field for 10/100 Mbps Mode ...................................................................................164
Table 78: Example of Splitting 10/100 Mbps Frame Data in Pattern Data Structure......................................164
Table 79: Firmware Mailbox Initialization........................................................................................................165
Table 80: Recommended Settings for PHY Auto-Negotiation ........................................................................165
Table 81: WOL Mode Clock Inputs .................................................................................................................166
Table 82: Magic Packet Detection Logic Enable ............................................................................................166
Table 83: PHY WOL Mode Control Registers.................................................................................................167
Table 84: Integrated MAC WOL Mode Control Registers...............................................................................168
Table 85: Transmit MAC Watermark Recommendation .................................................................................171
Table 86: Pause Quanta .................................................................................................................................171
Table 87: Keep_Pause Recommended Value................................................................................................172
Table 88: Statistic Block..................................................................................................................................172
Table 89: PHY Flow Control Registers ...........................................................................................................173
Table 90: Integrated MAC Flow Control Registers .........................................................................................174
Table 91: Interrupt-Related Registers.............................................................................................................178
Table 92: PCI Configuration Register Summary.............................................................................................186
Table 93: Vendor ID Register (Offset 0x00)....................................................................................................189
Table 94: Device ID Register (Offset 0x02) ....................................................................................................189
Table 95: Command Register (Offset 0x04) ...................................................................................................190
Table 96: Status Register (Offset 0x06)..........................................................................................................191
Table 97: Revision ID Register (Offset 0x08) .................................................................................................191
Table 98: Class Code Register (Offset 0x09) .................................................................................................192
Table 99: Cache Line Size Register (Offset 0x0C).........................................................................................192
Table 100: Latency Timer Register (Offset 0x0D) ..........................................................................................192
Table 101: Header Type Register (Offset 0x0E).............................................................................................192
Table 102: BIST Register (Offset 0x0F)..........................................................................................................193
Table 103: Base Address Register 1/2 (Offset 0x10) .....................................................................................193
Table 104: Subsystem Vendor ID Register (Offset 0x2C) ..............................................................................194
Table 105: Subsystem ID Register (Offset 0x2E) ...........................................................................................194
Table 106: Expansion ROM Base Address Register (Offset 0x30) ................................................................195
Table 107: Capabilities Pointer Register (Offset 0x34)...................................................................................195
Table 108: Interrupt Line Register (Offset 0x3C)............................................................................................195
Table 109: Minimum Grant Register (Offset 0x3E).........................................................................................196