Broadcom BCM5722 - Page 43

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page xliii
Table 110: Maximum Latency Register (Offset 0x3F).................................................................................... 196
Table 111: Power Management Capability Register (Offset 0x48) ................................................................ 197
Table 112: PM Next Capabilities Pointer Register (Offset 0x49).................................................................... 197
Table 113: Power Management Capabilities Register (Offset 0x4A) ............................................................. 197
Table 114: Power Management Control/Status Register (Offset 0x4C)......................................................... 198
Table 115: Power Management Data Register (Offset 0x4F) ........................................................................ 199
Table 116: VPD Capability ID Register (Offset 0x50)..................................................................................... 200
Table 117: VPD Next Capabilities Pointer Register (Offset 0x51).................................................................. 200
Table 118: VPD Flag and Address Register (Offset 0x52)............................................................................. 200
Table 119: VPD Data Register (Offset 0x54) ................................................................................................. 201
Table 120: MSI Capability ID Register (Offset 0x58)...................................................................................... 202
Table 121: Vendor-Specific Next Capabilities Pointer Register (Offset 0x59)................................................ 202
Table 122: Vendor-Specific Capabilities Length Register (Offset 0x5A)........................................................ 202
Table 123: Reset Counters Register (Offset 0x5C)........................................................................................ 202
Table 124: Device Serial No Lower DW Override Register (Offset: 0x60)..................................................... 203
Table 125: Device Serial No Upper DW Override Register (Offset: 0x64)..................................................... 203
Table 126: Miscellaneous Host Control Register (Offset 0x68)...................................................................... 204
Table 127: DMA Read/Write Control Register (Offset 0x6C) ......................................................................... 205
Table 128: PCI State Register (Offset 0x70).................................................................................................. 206
Table 129: PCI Clock Control Register........................................................................................................... 207
Table 130: Register Base Address Register (Offset 0x78)............................................................................. 209
Table 131: Memory Window Base Address Register (Offset 0x7C)............................................................... 210
Table 132: Register Data Register (Offset 0x80) ........................................................................................... 211
Table 133: Memory Window Data Register (Offset 0x84).............................................................................. 211
Table 134: Expansion ROM BAR Size Register (0x88) ................................................................................. 212
Table 135: Expansion ROM Address Register (Offset 0x8C) ........................................................................ 212
Table 136: Expansion ROM Data Register (0x90) ......................................................................................... 213
Table 137: VPD Interface Register (Offset 0x94)........................................................................................... 213
Table 138: UNDI Receive BD Standard Producer Ring Producer Index Mailbox (Offset 0x98)..................... 214
Table 139: UNDI Receive Return Ring Consumer Index Mailbox (Offset 0xA0)............................................ 214
Table 140: UNDI Send BD Producer Index Mailbox (Offset 0xA8) ................................................................ 214
Table 141: PCIe Capability ID Register (Offset 0xD0) ................................................................................... 215
Table 142: PCIe Next Capabilities Pointer Register (Offset 0xD1) ................................................................215
Table 143: PCIe Capabilities Register (Offset 0xD2) ..................................................................................... 215
Table 144: Device Capabilities Register (Offset 0xD4) .................................................................................. 216