Broadcom BCM5722 - Page 44

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page xliv Document 5722-PG101-R
Table 145: Device Control Register (Offset 0xD8)..........................................................................................217
Table 146: Device Status Register (Offset 0xDA)...........................................................................................218
Table 147: Link Capabilities Register (Offset 0xDC).......................................................................................219
Table 148: Link Control Register (Offset 0xE0) ..............................................................................................220
Table 149: Link Status Command Register (Offset 0xE2) ..............................................................................220
Table 150: MSI Capability ID Register (Offset 0xE8)......................................................................................221
Table 151: MSI Next Capabilities Pointer Register (Offset 0xE9)...................................................................221
Table 152: Message Control Register (Offset 0xEA)......................................................................................222
Table 153: Message Address Register (Offset 0xEC)....................................................................................223
Table 154: Message Data Register (Offset 0xF4) ..........................................................................................223
Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0x100)........................224
Table 156: Uncorrectable Error Status Register (Offset 0x104) .....................................................................224
Table 157: Uncorrectable Error Mask Register (Offset 0x108).......................................................................225
Table 158: Uncorrectable Error Severity Register (Offset 0x10C)..................................................................226
Table 159: Correctable Error Status Register (Offset 0x110).........................................................................227
Table 160: Correctable Error Mask Register (Offset 0x114)...........................................................................227
Table 161: Advanced Error Capabilities and Control Register (Offset 0x118)................................................227
Table 162: Virtual Channel Enhanced Capability Header (Offset 0x13c).......................................................228
Table 163: Port VC Capability Register (Offset 0x140) ..................................................................................228
Table 164: Port VC Capability Register 2 (Offset 0x144) ...............................................................................228
Table 165: Port VC Control Register (Offset 0x148).......................................................................................228
Table 166: Port VC Status Register (Offset 0x14A)........................................................................................229
Table 167: VC Resource Capability Register (Offset 0x14C).........................................................................229
Table 168: VC Resource Control Register (Offset 0x150)..............................................................................229
Table 169: VC Resource Status Register (Offset 0x156) ...............................................................................229
Table 170: Device Serial No Enhanced Capability Header Register (Offset 0x160) ......................................230
Table 171: Device Serial No Lower DW Register (Offset 0x164) ...................................................................230
Table 172: Device Serial No Upper DW Register (Offset 0x168) ...................................................................231
Table 173: Power Budgeting Enhanced Capability Header Register (Offset 0x16C) .....................................231
Table 174: Power Budgeting Data Select Register (Offset 0x170).................................................................231
Table 175: Power Budgeting Data Register (Offset 0x174)............................................................................232
Table 176: Power Budgeting Capability Register (Offset 0x178)....................................................................232
Table 177: Firmware Power Budgeting Register 1 (Offset 0x17C).................................................................233
Table 178: Firmware Power Budgeting Register 2 (Offset 0x17E).................................................................233
Table 179: Firmware Power Budgeting Register 3 (Offset 0x180)..................................................................234