Broadcom BCM5722 - Page 50

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page l Document 5722-PG101-R
BCM5757, BCM5754, BCM5787 Only ............................................................................................306
Table 300: MBUF Pool Base Address Register (Offset 0x4408)....................................................................307
Table 301: MBUF Pool Length Register (Offset 0x440C)...............................................................................307
Table 302: RX RISC MBUF Allocation Request Register (Offset 0x441C).....................................................308
Table 303: BM Hardware Diagnostic 1 Register (Offset 0x444C)...................................................................309
Table 304: BM Hardware Diagnostic 2 Register (Offset 0x4450)...................................................................309
Table 305: BM Hardware Diagnostic 3 Register (Offset 0x4454)...................................................................310
Table 306: Receive Flow Threshold Register (Offset 0x4458) .......................................................................310
Table 307: Read DMA Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757,
BCM5754, BCM5787 Only ..............................................................................................................311
Table 308: Read DMA Control Registers—BCM5906 Only............................................................................311
Table 309: Read DMA Mode Register (Offset 0x4800) ..................................................................................311
Table 310: Read DMA Status Register (Offset 0x4804).................................................................................313
Table 311: Read DMA Programmable IPv6 Extension Header Register (Offset: 0x4808).............................313
Table 312: Write DMA Control Registers........................................................................................................314
Table 313: Write DMA Mode Register (Offset 0x4C00)..................................................................................314
Table 314: Write DMA Status Register (Offset 0x4C04).................................................................................315
Table 315: RX RISC Registers .......................................................................................................................317
Table 316: RX RISC Mode Register Fields (Offset 0x5000)...........................................................................317
Table 317: RX RISC State Fields (Offset 0x5004)..........................................................................................318
Table 318: RX RISC Hardware Breakpoint Register (offset 0x5034) .............................................................320
Table 319: Virtual CPU Registers...................................................................................................................321
Table 320: VCPU Status Register Fields (Offset 0x5100) ..............................................................................321
Table 321: VCPU Status Register Fields (Offset 0x5100) ..............................................................................322
Table 322: RX RISC State Fields (Offset 0x5104)..........................................................................................322
Table 323: VCPU Holding Register (Offset 0x5108).......................................................................................322
Table 324: VCPU Data Register (Offset 0x510C)...........................................................................................322
Table 325: Virtual CPU Debug Register Fields (Offset 0x5110).....................................................................323
Table 326: Virtual CPU Debug Register Fields (Offset 0x5110).....................................................................323
Table 327: Virtual CPU Debug Register Fields (Offset 0x5110).....................................................................323
Table 328: Low-Priority Mailbox Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757,