Broadcom BCM5722 - Page 51

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page li
BCM5754, BCM5787 Only.............................................................................................................. 324
Table 329: Low-Priority Mailbox Registers—BCM5906 Only ......................................................................... 324
Table 330: Flow-Through Queues Registers.................................................................................................. 326
Table 331: FTQ Reset Register (Offset 0x5C00) ........................................................................................... 326
Table 332: MAC TX FIFO Enqueue Register (Offset 0x5CB8) ...................................................................... 327
Table 333: RXMBUF Cluster Free Enqueue Register (Offset 0x5CC8)......................................................... 328
Table 334: RDIQ FTQ Write/Peek Register (Offset 0x5CFC) ........................................................................ 328
Table 335: Functional Truth Table for the Combination of the Valid, Skip, and Pass Bits ............................. 329
Table 336: Message Signaled Registers........................................................................................................ 330
Table 337: MSI Mode Register (Offset 0x6000)............................................................................................. 330
Table 338: MSI Status Register (Offset 0x6004)............................................................................................ 330
Table 339: MSI FIFO Access Register (Offset 0x6008) ................................................................................. 331
Table 340: General Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754,
BCM5787 Only................................................................................................................................ 332
Table 341: General Control Registers—BCM5906 Only................................................................................ 332
Table 342: Mode Control Register (Offset 0x6800)........................................................................................ 333
Table 343: Miscellaneous Configuration Register (Offset 0x6804) ................................................................ 335
Table 344: Miscellaneous Local Control Register (Offset 0x6808) ................................................................ 336
Table 345: Timer Register (Offset 0x680C).................................................................................................... 337
Table 346: RX-RISC Event Register (Offset 0x6810)—BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757, BCM5754, BCM5787 Only............................................................................................ 338
Table 347: RX-RISC Event Register (Offset 0x6810)—BCM5906 Only ........................................................ 339
Table 348: RX-RISC Timer Reference Register (Offset 0x6814)................................................................... 340
Table 349: RX-RISC Semaphore Register (Offset 0x6818)...........................................................................340
Table 350: Serial EEPROM Address Register (Offset 0x6838) ..................................................................... 341
Table 351: Serial EEPROM Data Register (Offset 0x683C) ..........................................................................341
Table 352: Serial EEPROM Control Register (Offset 0x6840).......................................................................341
Table 353: MDI Control Register (Offset 0x6844) .......................................................................................... 342
Table 354: RX CPU Event Enable Register (Offset 0x684C)—BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757, BCM5754, BCM5787 Only............................................................................................ 343
Table 355: RX CPU Event Enable Register (Offset 0x684C)—BCM5906 Only............................................. 344
Table 356: Wake-on-LAN Registers............................................................................................................... 345
Table 357: WOL Mode Register (Offset 0x6880) ........................................................................................... 345
Table 358: WOL Config Register (Offset 0x6884).......................................................................................... 345
Table 359: WOL State Machine Status Register (Offset 0x6888).................................................................. 346
Table 360: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—