Broadcom BCM5722 - Page 52

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page lii Document 5722-PG101-R
BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only ..............347
Table 361: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—BCM5906 Only........................347
Table 362: Fast Boot Program Counter Register (Offset 0x6894)..................................................................348
Table 363: Chip Mode Register (Offset: 0x6898) ...........................................................................................349
Table 364: Energy Detect Timer Register (Offset: 0x689C) ...........................................................................350
Table 365: Miscellaneous Clock Control Register (Offset: 0x68A0) ...............................................................351
Table 366: Power Management Debug Register (Offset: 0x68A4).................................................................352
Table 367: Energy_Det Control Register (Offset: 0X68B0) ............................................................................353
Table 368: ASF Support Registers .................................................................................................................355
Table 369: ASF Control Register (Offset 0x6C00)..........................................................................................356
Table 370: SMBus Input Register (Offset 0x6C04).........................................................................................357
Table 371: SMBus Output Register (Offset 0x6C08)......................................................................................358
Table 372: ASF Watchdog Timer Register (Offset 0x6C0C) ..........................................................................359
Table 373: ASF Heartbeat Timer Register (Offset 0x6C10) ...........................................................................359
Table 374: Poll ASF Timer Register (Offset 0x6C14).....................................................................................360
Table 375: Poll Legacy Timer Register (Offset 0x6C18).................................................................................360
Table 376: Retransmission Timer Register (Offset 0x6C1C)..........................................................................360
Table 377: Time Stamp Counter Register (Offset 0x6C20) ............................................................................360
Table 378: SMBus Driver Select Register (Offset 0x6C24) ............................................................................361
Table 379: ASF RNG Command Register (0x6c30).......................................................................................361
Table 380: ASF RNG Data Register (0x6C34) ...............................................................................................361
Table 381: Auxiliary SMBus Master Status Register (Offset 0x6C40)............................................................362
Table 382: Auxiliary SMBus Master Control Register (Offset 0x6C44)...........................................................363
Table 383: Auxiliary SMBus Master Command Register (Offset 0x6C48)......................................................364
Table 384: Auxiliary SMBus Block Data Register (Offset 0x6C4C)................................................................364
Table 385: Auxiliary SMBus Slave Address/Control Register (Offset 0x6C50) ..............................................365
Table 386: Auxiliary SMBus Slave Status Register (Offset 0x6C54)..............................................................365
Table 387: Auxiliary SMBus Slave Data Register (Offset 0x6C58).................................................................366
Table 388: SMBus ARP Command Register (Offset 0x6C60)........................................................................366
Table 389: SMBus ARP Status Register (Offset 0x6C64) ..............................................................................367
Table 390: UDID Register 0 (Offset 0x6C68) .................................................................................................367
Table 391: UDID Register 1 (Offset 0x6C6C).................................................................................................368
Table 392: UDID Register 2 (Offset 0x6C70) .................................................................................................368
Table 393: UDID Register 3 (Offset 0x6C74) .................................................................................................368
Table 394: Non-Volatile Memory Interface Registers .....................................................................................369