Broadcom BCM5722 - Page 53

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page liii
Table 395: NVM Command Register (Offset 0x7000).................................................................................... 370
Table 396: NVM Status Register (0x7004H) .................................................................................................. 370
Table 397: NVM Write Register (Offset 0x7008)............................................................................................ 371
Table 398: NVM Address Register (Offset 0x700C)....................................................................................... 371
Table 399: NVM Read Register (Offset 0x7010)............................................................................................ 371
Table 400: NVM Config 1 Register (Offset 0x7014)....................................................................................... 372
Table 401: NVM Config 2 Register (Offset 0x7018)....................................................................................... 373
Table 402: NVM Config 3 Register (Offset 0x701C) ...................................................................................... 374
Table 403: Software Arbitration Register (Offset 0x7020).............................................................................. 374
Table 404: NVM Access Register (Offset 0x7024)......................................................................................... 375
Table 405: NVM Write1 Register (Offset 0x7028).......................................................................................... 376
Table 406: NVM Arbitration Watchdog Timer Register (Offset 0x702C)........................................................ 376
Table 407: NVM Auto-Sense Status Register (0x7038h)............................................................................... 377
Table 408: BIST Registers ............................................................................................................................. 378
Table 409: BIST Control Register (Offset 0x7400)......................................................................................... 378
Table 410: BIST Status Register (Offset 0x7404) .......................................................................................... 378
Table 411: BIST Status Register (Offset 0x7404) .......................................................................................... 379
Table 412: PCIe Registers ............................................................................................................................. 381
Table 413: TLP Control Register (Offset 0x7C00).......................................................................................... 383
Table 414: Transaction Configuration Register (0x7C04) .............................................................................. 384
Table 415: Write DMA Request Upper Address Diagnostic Register (Offset 0x7C10) .................................. 387
Table 416: Write DMA Request Lower Address Diagnostic Register (Offset 0x7C14) .................................. 387
Table 417: Write DMA Length/Byte Enable and Request Diagnostic Register (Offset 0x7C18).................... 388
Table 418: Read DMA Request Upper Address Diagnostic Register (Offset 0x7C1C) ................................. 388
Table 419: Read DMA Request Lower Address Diagnostic Register (Offset 0x7C20).................................. 388
Table 420: Read DMA Length and Request Diagnostic Register (Offset 0x7C24)........................................ 388
Table 421: MSI DMA Request Upper Address Diagnostic Register (Offset 0x7C28) .................................... 389
Table 422: MSI DMA Request Lower Address Diagnostic Register (Offset 0x7C2C).................................... 389
Table 423: MSI DMA Length and Request Diagnostic Register (Offset 0x7C30) .......................................... 389
Table 424: Slave Request Length and Type Diagnostic Register (Offset 0x7C34)........................................ 390
Table 425: Flow Control Inputs Diagnostic Register (Offset 0x7C38)............................................................ 390
Table 426: XMT State Machines and Gated Requests Diagnostic Register (Offset 0x7C3C)....................... 391
Table 427: Address ACK Xfer Count and ARB Length Diagnostic Register (Offset 0x7C40)........................ 391
Table 428: DMA Completion Header Diagnostic Register 0 (Offset 0x7C44)................................................ 391
Table 429: DMA Completion Header Diagnostic Register 1 (Offset 0x7C48)................................................ 392