Mips Technologies R4000 - Page 177

MIPS R4000 Microprocessor User's Manual 147
CPU Exception Processing
Figure 5-20 TLB/XTLB Miss Exception Handler (HW)
EXL <- 1
PC <- 0xFFFF FFFF BFC0 0200 + Vec.Off.
PC <- 0xFFFF FFFF 8000 0000 + Vec.Off.
=0 (normal) =1
To TLB/XTLB Exception Servicing Guidelines
(unmapped, cached) (unmapped, uncached)
BEV
(SR bit 22)
XTLB
N
Y
Vec. Off. = 0x000Vec. Off. = 0x080 Vec. Off. = 0x180
Instr. in
Yes
Processor forced to Kernel Mode &
Check if exception within
(bootstrap)
Br.Dly. Slot?
EXL
(SR bit 1)
=1
=0
Instruction?
Points to General Exception
Points to Refill Exception
No
Set Cause Reg.
EnHi <- VPN2, ASID
Context <- VPN2
EXCCode, CE and
Set Cause Reg.
EnHi <- VPN2, ASID
Context <- VPN2
EXCCode, CE and
Cause bit 31 (BD) <- 0
EPC <- PC
EPC <- (PC - 4)
Set BadVA
Set BadVA
another exception
interrupt disabled
EXL
(SR bit 1)
=1
=0
Cause bit 31 (BD) <- 1