MIPS R4000 Microprocessor User's Manual A-13
CPU Instruction Set Details
Format:
ADDIU rt, rs, immediate
Description:
The 16-bit immediate is sign-extended and added to the contents of general
register rs to form the result. The result is placed into general register rt.
No integer overflow exception occurs under any circumstances. In 64-bit
mode, the operand must be valid sign-extended, 32-bit values.
The only difference between this instruction and the ADDI instruction is
that ADDIU never causes an overflow exception.
Operation:
Exceptions:
None
ADDIU
Add Immediate Unsigned
31 2526 2021 1516 0
ADDIU
rs rt
immediate
655 16
0 0 1 0 0 1
ADDIU
32 T: GPR [rt] ← GPR[rs] + (immediate
15
)
16
|| immediate
15...0
64 T: temp ← GPR[rs] + (immediate
15
)
48
|| immediate
15...0
GPR[rt] ← (temp
31
)
32
|| temp
31...0
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