Appendix A
A-14 MIPS R4000 Microprocessor User's Manual
Format:
ADDU rd, rs, rt
Description:
The contents of general register rs and the contents of general register rt
are added to form the result. The result is placed into general register rd.
No overflow exception occurs under any circumstances. In 64-bit mode,
the operands must be valid sign-extended, 32-bit values.
The only difference between this instruction and the ADD instruction is
that ADDU never causes an overflow exception.
Operation:
Exceptions:
None
ADDU
Add Unsigned
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 ADDU
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
ADDU
32 T: GPR[rd] ←GPR[rs] + GPR[rt]
64 T: temp ← GPR[rs] + GPR[rt]
GPR[rd] ← (temp
31
)
32
|| temp
31...0
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