Appendix A
A-44 MIPS R4000 Microprocessor User's Manual
Bits 20...18 (this value is listed under the Code column) of the instruction
specify the operation as follows:
Code Caches Name Operation
0 I, SI
Index
Invalidate
Set the cache state of the cache block to Invalid.
0D
Index
Writeback
Invalidate
Examine the cache state and Writeback bit (
W
bit) of the primary data
cache block at the index specified by the virtual address. If the state is
not Invalid and the
W
bit is set, write the block back to the secondary
cache (if present) or to memory (if no secondary cache). The address to
write is taken from the primary cache tag. When a secondary cache is
present, and the
CE
bit of the
Status
register is set, the contents of the
ECC
register is XOR’d into the computed check bits during the write to
the secondary cache for the addressed doubleword. Set the cache state
of primary cache block to Invalid. The
W
bit is unchanged (and irrelevant
because the state is Invalid).
OSD
Index
Writeback
Invalidate
Examine the cache state of the secondary data cache block at the index
specified by the physical address. If the block is dirty (the state is Dirty
Exclusive or Dirty Shared), write the data back to memory. Like all
secondary writebacks, the operation writes any modified data for the
addresses from the primary data cache. The address to write is taken
from the secondary cache tag. The
PIdx
field of the secondary tag is
used to determine the locations in the primaries to check for matching
primary blocks. In all cases, set the state of the secondary cache block
and all matching primary subblocks to Invalid. No Invalidate is sent on
the R4000’s system interface.
1 All
Index Load
Tag
Read the tag for the cache block at the specified index and place it iinto
the
TagLo
and
TagHi
CP0 registers, ignoring any ECC or parity errors.
Also load the data ECC or parity bits into the ECC register.
2 All
Index Store
Tag
Write the tag for the cache block at the specified index from the
TagLo
and
TagHi
CP0 registers. The processor uses computed parity for the
primary caches and the
TagLo
register in the case of the secondary
cache.
CACHE
CACHE
(continued)
ache
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