Appendix A
A-46 MIPS R4000 Microprocessor User's Manual
Code Caches Name Operation
5SD
Hit Writeback
Invalidate
If the cache block contains the specified address, write back the data (if
dirty), and mark the secondary cache block and all matching blocks in
both primary caches invalid. As usual with secondary writebacks,
modified data in the primary data cache (matching block with the
W
bit
set) is used during the writeback. The
PIdx
field of the secondary tag is
used to determine the locations in the primaries to check for matching
primary blocks. The
CH
bit in the
Status
register is set or cleared to
indicate a hit or miss.
5 I Fill
Fill the primary instruction cache block from secondary cache or memory.
If the
CE
bit of the Status register is set, the content of the
ECC
register
is used instead of the computed parity bits for addressed doubleword
when written to the instruction cache. For the R4000PC, the cache is
filled from memory. For the R4000SC and R4000MC, the cache is filled
from the secondary cache whether or not the secondary cache block is
valid or contains the specified address.
6 D Hit Writeback
If the cache block contains the specified address, and the
W
bit is set,
write back the data. The
W
bit is not cleared; a subsequent miss to the
block will write it back again. This second writeback is redundant, but not
incorrect. When a secondary cache is present, and the
CE
bit of the
Status
register is set, the content of the
ECC
register is XOR’d into the
computed check bits during the write to the secondary cache for the
addressed doubleword. Note: The
W
bit is not cleared during this
operation due to an artifact of the implementation; the
W
bit is
implemented as part of the data side of the cache array so that it can be
written during a data write.
6 SD Hit Writeback
If the cache block contains the specified address, and the cache state is
Dirty Exclusive or Dirty Shared, data is written back to memory. The
cache state is unchanged; a subsequent miss to the block causes it to be
written back again. This second writeback is redundant, but not
incorrect. The
CH
bit in the
Status
register is set or cleared to indicate a
hit or miss. The writeback looks in the primary data cache for modified
data, but does not invalidate or clear the Writeback bit in the primary data
cache. Note: The state of the secondary block is not changed to clean
during this operation because the
W
bit of matching sub-blocks cannot
be cleared to put the primary block in a clean state.
6 I Hit Writeback
If the cache block contains the specified address, data is written back
unconditionally. When a secondary cache is present, and the
CE
bit of
the
Status
register is set, the contents of the
ECC
register is XOR’d into
the computed check bits during the write to the secondary cache for the
addressed doubleword.
CACHE
CACHE
(continued)
ache
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