MIPS R4000 Microprocessor User's Manual A-47
CPU Instruction Set Details
Operation:
Exceptions:
Coprocessor unusable exception
Code Caches Name Operation
7 SI,SD Hit Set Virtual
This operation is used to change the virtual index of secondary cache
contents, avoiding unnecessary memory operations. If the cache block
contains the specified address, invalidate matching blocks in the primary
caches at the index formed by concatenating
PIdx
in the secondary
cache tag (not the virtual address of the operation) and vAddr
11..4
, and
then set the virtual index field of the secondary cache tag from the
specified virtual address. Modified data in the primary data cache is not
preserved by the operation and should be explicitly written back before
this operation. The
CH
bit in the
Status
register is set or cleared to
indicate a hit or miss.
CACHE
CACHE
(continued)
ache
32, 64 T: vAddr ā ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ā AddressTranslation (vAddr, DATA)
CacheOp (op, vAddr, pAddr)
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