MIPS R4000 Microprocessor User's Manual A-63
CPU Instruction Set Details
Format:
DMULT rs, rt
Description:
The contents of general registers rs and rt are multiplied, treating both
operands as 2’s complement values. No integer overflow exception occurs
under any circumstances.
When the operation completes, the low-order word of the double result is
loaded into special register LO, and the high-order word of the double
result is loaded into special register HI.
If either of the two preceding instructions is MFHI or MFLO, the results of
these instructions are undefined. Correct operation requires separating
reads of HI or LO from writes by a minimum of two other instructions.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DMULT
Doubleword Multiply
31 2526 2021 1516 0
rs rt
655
65
10 6
SPECIAL 0 DMULT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
DMULT
64 T–2: LO ← undefined
HI ← undefined
T–1: LO ← undefined
HI ← undefined
T: t ← GPR[rs] * GPR[rt]
LO ← t
63...0
H I ← t
127...64
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