Appendix A
A-64 MIPS R4000 Microprocessor User's Manual
Format:
DMULTU rs, rt
Description:
The contents of general register rs and the contents of general register rt
are multiplied, treating both operands as unsigned values. No overflow
exception occurs under any circumstances.
When the operation completes, the low-order word of the double result is
loaded into special register LO, and the high-order word of the double
result is loaded into special register HI.
If either of the two preceding instructions is MFHI or MFLO, the results of
these instructions are undefined. Correct operation requires separating
reads of HI or LO from writes by a minimum of two instructions.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DMULTU
ou
ewor
u
t
p
y
31 2526 2021 1516 0
rs rt
655
65
10 6
SPECIAL 0 DMULTU
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
DMULTU
Unsigned
64 T–2: LO ← undefined
HI ← undefined
T–1: LO ← undefined
HI ← undefined
T: t ← (0 || GPR[rs]) * (0 || GPR[rt])
LO ← t
63...0
HI ←t
127...64
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