MIPS R4000 Microprocessor User's Manual A-65
CPU Instruction Set Details
Format:
DSLL rd, rt, sa
Description:
The contents of general register rt are shifted left by sa bits, inserting zeros
into the low-order bits. The result is placed in register rd.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DSLL
Doubleword Shift Left Logical
31 2526 2021 1516
SPECIAL 0 rt
655
rd sa DSLL
55 6
11 10 6 5 0
0 0 0 0 0 0 1 1 1 0 0 0
DSLL
0 0 0 0 0
64 T: s ← 0 || sa
GPR[rd] ← GPR[rt]
(63–s)...0
|| 0
s
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