Appendix A
A-66 MIPS R4000 Microprocessor User's Manual
Format:
DSLLV rd, rt, rs
Description:
The contents of general register rt are shifted left by the number of bits
specified by the low-order six bits contained in general register rs,
inserting zeros into the low-order bits. The result is placed in register rd.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DSLLV
Doubleword Shift Left
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 DSLLV
55 6
11 10 6 5 0
0 0 0 0 0 0 0 1 0 1 0 00 0 0 0 0
DSLLV
Logical Variable
64 T: s ← GPR[rs]
5...0
GPR[rd]← GPR[rt]
(63–s)...0
|| 0
s
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