Mips Technologies R4000 - Page 545

MIPS R4000 Microprocessor User's Manual A-77
CPU Instruction Set Details
Format:
J target
Description:
The 26-bit target address is shifted left two bits and combined with the
high-order bits of the address of the delay slot. The program
unconditionally jumps to this calculated address with a delay of one
instruction.
Operation:
Exceptions:
None
J
Jump
31 2526
J
6
0
target
26
0 0 0 0 1 0
J
32 T: temp ← target
T+1: PC ← PC
31...28
|| temp || 0
2
64 T: temp ← target
T+1: PC ← PC
63...28
|| temp || 0
2