Mips Technologies R4000 - Page 546

Appendix A
A-78 MIPS R4000 Microprocessor User's Manual
Format:
JAL target
Description:
The 26-bit target address is shifted left two bits and combined with the
high-order bits of the address of the delay slot. The program
unconditionally jumps to this calculated address with a delay of one
instruction. The address of the instruction after the delay slot is placed in
the link register, r31.
Operation:
Exceptions:
None
JAL
Jump And Link
31 2526
JAL
6
0
target
26
0 0 0 0 1 1
JAL
GPR[31] ← PC + 8
32 T: temp ← target
T+1: PC ← PC
31...28
|| temp || 0
2
GPR[31] ← PC + 8
64 T: temp ← target
T+1: PC ← PC
63...28
|| temp || 0
2