Mips Technologies R4000 - Page 553

MIPS R4000 Microprocessor User's Manual A-85
CPU Instruction Set Details
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Coprocessor unusable exception
Opcode Bit Encoding:
(continued)
LDCz
Load Doubleword To Coprocessor
LDCz
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
COPzLD (rt, mem)
COPzLD (rt, mem)
LDCz
101011
31 30 29 28 27 26
Bit #
0
LDC1
101101
31 30 29 28 27 26
Bit #
0
LDC2
Coprocessor Unit Number
Opcode