MIPS R4000 Microprocessor User's Manual A-87
CPU Instruction Set Details
The contents of general register rt are internally bypassed within the
processor so that no NOP is needed between an immediately preceding
load instruction which specifies register rt and a following LDL (or LDR)
instruction which also specifies register rt.
No address exceptions due to alignment are possible.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
(continued)
LDL
Load Doubleword Left
LDL
endif
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
pAddr ← pAddr
PSIZE–1...3
|| 0
3
GPR[rt] ← mem
7+8*byte...0
|| GPR[rt]
55–8*byte...0
mem ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
if BigEndianMem = 0 then
byte ← vAddr
2...0
xor BigEndianCPU
3
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