Mips Technologies R4000 - Page 574

Appendix A
A-106 MIPS R4000 Microprocessor User's Manual
The contents of general register rt are internally bypassed within the
processor so that no NOP is needed between an immediately preceding
load instruction which specifies register rt and a following LWR (or LWL)
instruction which also specifies register rt. No address exceptions due to
alignment are possible.
Operation:
(continued)
LWR
Load Word Right
LWR
pAddr ← pAddr
PSIZE–31...3
|| 0
3
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
endif
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
pAddr ← pAddr
PSIZE–31...3
|| 0
3
GPR[rt] ← (temp
31
)
32
|| temp
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
if BigEndianMem = 1 then
byte ← vAddr
1...0
xor BigEndianCPU
2
word ← vAddr
2
xor BigEndianCPU
temp ← GPR[rt]
31...32-8*byte
|| mem
31+32*word...32*word+8*byte
endif
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
GPR[rt] ← temp
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
if BigEndianMem = 1 then
byte ← vAddr
1...0
xor BigEndianCPU
2
word ← vAddr
2
xor BigEndianCPU
temp ← GPR[rt]
31...32-8*byte
|| mem
31+32*word...32*word+8*byte