MIPS R4000 Microprocessor User's Manual A-107
CPU Instruction Set Details
Given a word in a register and a word in memory, the operation of LWR
is as follows:
LEM Little-endian memory (BigEndianMem = 0)
BEM BigEndianMem = 1
Type AccessType (see Table 2-1) sent to memory
Offset pAddr
2...0
sent to memory
S sign-extend of destination
31
X either unchanged or sign-extend of destination
31
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
LWR
LWR
(continued)
Load Word Right
LWR
ACDB
Register
IKLJ
Memory
EGHF
MOPN
0 SSSSMNOP 0 0 4 XXXXEFGI 0 7 0
1 XXXXEMNO 1 1 4 XXXXEFI J 1 6 0
2 XXXXEFMN 2 2 4 XXXXEI J K 2 5 0
3 XXXXEFGM 3 3 4 SSSSI JKL 3 4 0
4 SSSSI JKL 0 4 0 XXXXEFGM 0 3 4
5 XXXXEI JK 1 5 0 XXXXEFMN 1 2 4
6 XXXXEFI J 2 6 0 XXXXEMNO 2 1 4
7 XXXXEFGI 3 7 0 SSSSMNOP 3 0 4
BigEndianCPU = 0
vAddr
2..0
destination
destination
type
type
offset
offset
BigEndianCPU = 1
LEM BEM
LEM BEM
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