Appendix A
A-108 MIPS R4000 Microprocessor User's Manual
Format:
LWU rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the word at the
memory location specified by the effective address are loaded into general
register rt. The loaded word is zero-extended.
If either of the two least-significant bits of the effective address is non-zero,
an address error exception occurs.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit mode)
LWU
Load Word Unsigned
31 2526 2021 1516 0
LWU base rt
offset
655 16
1 0 0 1 1 1
LWU
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← 0
32
|| mem
31+8*byte...8*byte
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
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