MIPS R4000 Microprocessor User's Manual A-109
CPU Instruction Set Details
Format:
MFC0 rt, rd
Description:
The contents of coprocessor register rd of the CP0 are loaded into general
register rt.
Operation:
Exceptions:
Coprocessor unusable exception
MFC0
Move From
rd
11 10
5
31 2526 2021 1516 0
COP0 MF rt
0
655 11
System Control Coprocessor
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MFC0
32 T: data ← CPR[0,rd]
T+1: GPR[rt] ← data
64 T: data ← CPR[0,rd]
T+1: GPR[rt] ← (data
31
)
32
|| data
31...0
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