Appendix A
A-114 MIPS R4000 Microprocessor User's Manual
Format:
MTC0 rt, rd
Description:
The contents of general register rt are loaded into coprocessor register rd
of CP0.
Because the state of the virtual address translation system may be altered
by this instruction, the operation of load instructions, store instructions,
and TLB operations immediately prior to and after this instruction are
undefined.
Operation:
Exceptions:
Coprocessor unusable exception
MTC0
ove
o
rd
11 10
5
31 2526 2021 1516 0
COP0 MT rt
0
655 11
System Control Coprocessor
0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00
MTC0
32, 64 T: data ā GPR[rt]
T+1: CPR[0,rd] ā data
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