Mips Technologies R4000 - Page 583

MIPS R4000 Microprocessor User's Manual A-115
CPU Instruction Set Details
Format:
MTCz rt, rd
Description:
The contents of general register rt are loaded into coprocessor register rd
of coprocessor z.
Operation:
Exceptions:
Coprocessor unusable exception
*Opcode Bit Encoding:
MTCz
11
Move To Coprocessor
31 2526 2021 1516
COPz MT rt
655
rd
0
5
11 10 0
0 1 0 0 x x* 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
MTCz
32 T: data ← GPR[rt]
T+1: CPR[z,rd] ← data
64 T: data ← GPR[rt]
31...0
T+1: if rd
0
= 0
CPR[z,rd
4...1
|| 0] ← CPR[z, rd
4...1
|| 0]
63...32
|| data
else
CPR[z,rd
4...1
|| 0] ← data || CPR[z,rd
4...1
|| 0]
31...0
endif
MTCz
000011
31 30 29 28 27 26
Bit #
25 0
C0P1
01000
24 23 22
21
000101
31 30 29 28 27 26
Bit #
25 0
C0P2
01000
24 23 22
21
Coprocessor Suboperation
000001
31 30 29 28 27 26
Bit #
25 0
C0P0
01000
24 23 22
21
Coprocessor Unit Number
Opcode