Mips Technologies R4000 - Page 595

MIPS R4000 Microprocessor User's Manual A-127
CPU Instruction Set Details
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
(continued)
SC
Store Conditional
SC
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
data ← GPR[rt]
63-8*byte...0
|| 0
8*byte
if LLbit then
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)
endif
GPR[rt] ← 0
31
|| LLbit
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
data ← GPR[rt]
63-8*byte...0
|| 0
8*byte
if LLbit then
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)
endif
GPR[rt] ← 0
63
|| LLbit