Appendix A
A-128 MIPS R4000 Microprocessor User's Manual
Format:
SCD rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of general register rt
are conditionally stored at the memory location specified by the effective
address.
If any other processor or device has modified the physical address since
the time of the previous Load Linked Doubleword instruction, or if an
ERET instruction occurs between the Load Linked Doubleword
instruction and this store instruction, the store fails and is inhibited from
taking place.
The success or failure of the store operation (as defined above) is indicated
by the contents of general register rt after execution of the instruction. A
successful store sets the contents of general register rt to 1; an unsuccessful
store sets it to 0.
The operation of Store Conditional Doubleword is undefined when the
address is different from the address used in the last Load Linked
Doubleword.
This instruction is available in User mode; it is not necessary for CP0 to be
enabled.
If either of the three least-significant bits of the effective address is non-
zero, an address error exception takes place.
SCD
Store Conditional Doubleword
31 2526 2021 1516 0
SCD base rt
offset
655 16
1 1 1 1 0 0
SCD
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