MIPS R4000 Microprocessor User's Manual A-129
CPU Instruction Set Details
If this instruction should both fail and take an exception, the exception
takes precedence.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit mode)
(continued)
SCD
ore
on
ona
ou
ewor
SCD
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
data ← GPR[rt]
if LLbit then
StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)
endif
GPR[rt] ← 0
63
|| LLbit
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