Appendix A
A-130 MIPS R4000 Microprocessor User's Manual
Format:
SD rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of general register rt
are stored at the memory location specified by the effective address.
If either of the three least-significant bits of the effective address are non-
zero, an address error exception occurs.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit user mode
R4000 in 32-bit supervisor mode)
SD
Store Doubleword
31 2526 2021 1516 0
SD base rt
offset
655 16
1 1 1 1 1 1
SD
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
data ← GPR[rt]
StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)
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