MIPS R4000 Microprocessor User's Manual A-131
CPU Instruction Set Details
Format:
SDCz rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. Coprocessor unit z sources a
doubleword, which the processor writes to the addressed memory
location. The data to be stored is defined by individual coprocessor
specifications.
If any of the three least-significant bits of the effective address are non-
zero, an address error exception takes place.
This instruction is not valid for use with CP0.
This instruction is undefined when the least-significant bit of the rt field is
non-zero.
Operation:
*See the table, “Opcode Bit Encoding” on next page, or “CPU Instruction
Opcode Bit Encoding” at the end of Appendix A.
SDCz
Store Doubleword
31 2526 2021 1516 0
SDCz base rt
offset
655 16
1 1 1 1 x x*
SDCz
From Coprocessor
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
data ← COPzSD(rt),
StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
data ← COPzSD(rt),
StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)
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