Mips Technologies R4000 - Page 607

MIPS R4000 Microprocessor User's Manual A-139
CPU Instruction Set Details
Format:
SH rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form an unsigned effective address. The least-significant
halfword of register rt is stored at the effective address. If the least-
significant bit of the effective address is non-zero, an address error
exception occurs.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
SH
Store Halfword
31 2526 2021 1516 0
SH base rt
offset
655 16
1 0 1 0 0 1
SH
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
data ← GPR[rt]
63–8*byte...0
|| 0
8*byte
StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA)
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
data ← GPR[rt]
63–8*byte...0
|| 0
8*byte
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))