Appendix A
A-140 MIPS R4000 Microprocessor User's Manual
Format:
SLL rd, rt, sa
Description:
The contents of general register rt are shifted left by sa bits, inserting zeros
into the low-order bits.
The result is placed in register rd.
In 64-bit mode, the 32-bit result is sign extended when placed in the
destination register. It is sign extended for all shift amounts, including
zero; SLL with a zero shift amount truncates a 64-bit value to 32 bits and
then sign extends this 32-bit value. SLL, unlike nearly all other word
operations, does not require an operand to be a properly sign-extended
word value to produce a valid sign-extended word result.
NOTE: SLL with a shift amount of zero may be treated as a NOP by
some assemblers, at some optimization levels. If using SLL with a
zero shift to truncate 64-bit values, check the assembler you are using.
Operation:
Exceptions:
None
SLL
Shift Left Logical
31 2526 2021 1516
SPECIAL rt
655
rd sa SLL
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0
SLL
0
0 0 0 0 0
32 T: GPR[rd] ← GPR[rt]
31– sa...0
|| 0
sa
64 T: s ← 0 || sa
temp ← GPR[rt]
31-s...0
|| 0
s
GPR[rd] ← (temp
31
)
32
|| temp
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