MIPS R4000 Microprocessor User's Manual A-151
CPU Instruction Set Details
Format:
SUBU rd, rs, rt
Description:
The contents of general register rt are subtracted from the contents of
general register rs to form a result.
The result is placed into general register rd.
In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
The only difference between this instruction and the SUB instruction is
that SUBU never traps on overflow. No integer overflow exception occurs
under any circumstances.
Operation:
Exceptions:
None
SUBU
Subtract Unsigned
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 SUBU
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
SUBU
32 T: GPR[rd] ← GPR[rs] – GPR[rt]
64 T: temp ← GPR[rs] - GPR[rt]
GPR[rd] ← (temp
31
)
32
|| temp
31...0
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