Mips Technologies R4000 - Page 620

Appendix A
A-152 MIPS R4000 Microprocessor User's Manual
Format:
SW rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of general register rt
are stored at the memory location specified by the effective address.
If either of the two least-significant bits of the effective address are non-
zero, an address error exception occurs.
Operation:
Exceptions:
TLB refill exception TLB invalid exception
TLB modification exception Bus error exception
Address error exception
SW
Store Word
31 2526 2021 1516 0
SW base rt
offset
655 16
1 0 1 0 1 1
SW
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
data ← GPR[rt]
63-8*byte
|| 0
8*byte
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
data ← GPR[rt]
63-8*byte
|| 0
8*byte
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)