Mips Technologies R4000 - Page 621

MIPS R4000 Microprocessor User's Manual A-153
CPU Instruction Set Details
Format:
SWCz rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. Coprocessor unit z sources a word,
which the processor writes to the addressed memory location.
The data to be stored is defined by individual coprocessor specifications.
This instruction is not valid for use with CP0.
If either of the two least-significant bits of the effective address is non-zero,
an address error exception occurs.
Operation:
*See the table “Opcode Bit Encoding” on next page, or “CPU Instruction
Opcode Bit Encoding” at the end of Appendix A.
SWCz
Store Word From Coprocessor
31 2526 2021 1516 0
SWCz
base rt
offset
655 16
1 1 1 0 x x*
SWCz
32 T: vAddr ← ((offset
15
)
16 ||
offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
data ← COPzSW (byte, rt)
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
data ← COPzSW (byte,rt)
StoreMemory (uncached, WORD, data, pAddr, vAddr DATA)