Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Firmware Download Page 94
RESET RISC PROCESSOR
The RX processor can be reset by setting the Reset RX RISC Bit of the RX RISC Mode register (see “RX RISC Mode
Register (Offset 0x5000)” on page 317). This bit is self-clearing bit; it will be cleared once internal reset of processor is
completed.
For example, to reset RX RISC, do the following:
WR 5004, 0xffffffff /* Clear all CPU state */
WR 0x5000, 0x1
Wait until Bit 0 of register at 0x5000 is cleared.
HALT RISC PROCEDURE
1. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register (see “RX RISC State Register
(Offset 0x5004)” on page 318).
2. Issue RX RISC halt. Write the RISC_MODE_HALT bit to the RX_RISC_Mode register (see “RX RISC Mode Register
(Offset 0x5000)” on page 317).
3. Read/verify that the RISC_MODE_HALT bit is set. Read the Rx RISC_MODE_HALT bit back from the RX_RISC_Mode
register. Break from procedure if bit is set.
4. Delay 10 µs and jump to step 1. Repeat the procedure up to 10,000 times.
START RISC PROCEDURE
This procedure first stops the RX RISC and modifies the program counter. The RISC processor is then started to begin
executing firmware at new address given by program counter.
1. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register (see “RX RISC State Register
(Offset 0x5004)” on page 318).
2. Set the RX RISC program counter. Write t3FwTextAddr to the RX_RISC_PC register (see“RX RISC Program Counter
(Offset 0x501C)” on page 320).
3. Read back the PC register. Read the RX_RISC_PC register and verify that t3FwTextAddr is set. If properly set, then
jump to Step 7.
4. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register.
5. Halt the RX RISC. Write the RISC_MODE_HALT bit to the RX_RISC_Mode register.
6. Delay one millisecond. Jump to Step 2. and repeat procedure.
7. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register.
8. Clear the RX RISC mode register. Write 0x00 to the RX_RISC_Mode register (see “RX RISC Program Counter (Offset
0x501C)” on page 320).
Note: The t3FwTextAddr should not be converted to a register relative address. The RISCs execute from
a local memory space. The conversion is only necessary for writing t3FwText [] to the scratch pad using
register space—the host view of the scratch pad region is different from the RISC view. See Table 41 on
page 93.
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