BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 95 Firmware Download Document 5722-PG101-R
FIRMWARE DOWNLOAD PROCEDURE
The host driver should use register indirect access to modify both the scratch pad and RISC register space. See
“Pseudocode” on page 132 in Section 9: “PCI”.
1. Halt the RX RSIC Core (see “Halt RISC Procedure” on page 94).
2. Clear the RX RISC Scratch pad. Use register indirect access and write zero(s) starting at register address 0x30000 (see
Table 41 on page 93). The last address to clear is 0x33FFF. The total length of the scratch pad is 0x4000 and the host
driver should increment the target address by four (4), since each MIPS word is 32 bits (4 bytes).
3. Convert variable t3FwRodataAddr to a register relative address for the RX RISC. The register address is calculated as
follows:
regNormalized = 0x10000 + (t3FwTextAddr & 0xFFFF)
For systems using RXMBUF memory for firmware, ensure that the downloaded firmware does not overlap the MBUF
Pool Address (see “MBUF Pool Base Address Register (Offset 0x4408)” on page 307).
4. Write the array t3FwText [] to the RX scratched/RXMBUF (see Table 41 on page 93). Use register indirect access and
increment by four bytes for every 32-bit write. The last/limit address to write is calculated as follows:
regNormalized + t3FwTextLen
5. Convert variable t3FwRodataAddr to a register relative address for the RX RISC. The register address is calculated as
follows:
regNormalized = 0x10000 + (t3FwRoDataAddr & 0xFFFF)
6.
Write the array t3FwRodata [] to the RX scratch pad/RXMBUF (see Table 41 on page 93). Use register indirect access
and increment by four bytes for every 32-bit write. The last/limit address to write is calculated as follows:
regNormalized (from Step 5.) + t3FwRodataLen
7.
Convert variable t3FwDataAddr to a register relative address for the RX RISC. The register address is calculated as
follows:
regNormalized = 0x10000 + (t3FwDataAddr & 0xFFFF)
8. Write the array t3FwData [] to the RX scratch pad/RXMBUF (see Table 41 on page 93). Use register indirect access and
increment by four bytes for every 32-bit write. The last/limit address to write is calculated as follows:
regNormalized (from Step 7.) + t3FwDataLen
9.
Start the RX RISC (see “Start RISC Procedure” on page 94).
When freeing received RxMbufs (e.g., received ASF RMCP packets) from the MIPS CPU (running ASF firmware or any other
optional FW) while simultaneously receiving/freeing TCP traffic for the host device driver, a race condition can occur which
causes subsequent receives to fail (no more RxMbufs get enqueued). To avoid this race condition, before freeing the
RxMbuf chain (by writing to the MbufClustFreeFtqFifoEnqueueDequeue register, 0x5cc8), the FW should poll the buffer
manager hardware diagnostic 3 register (0x4454) until the descriptor in bits 25:16 matches the MBUF cluster at the
beginning of the chain we're about to free. Also, note that the hardware diagnostic register uses a cluster based on the offset
from the top of the RxMbuf pool (e.g., 0x16000) and the firmware uses a cluster based on the offset from 0x10000, so some
calculations must be performed to compare the proper pointer values.
Note: When enabled, the ASF/IPMI FW is required to run even in the absence of OS. The IPMI/ASF FW is
normally programmed into NVRAM and the bootcode will load this FW into scratch pad/RxMbuf memory if
the IPMI/ASF feature is enabled. The bootcode reserves enough memory out of RxMbuf as RISC scratch
pad for IPMI/ASF firmware.
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