Cisco ASR 9000 Series - Page 1132

DescriptionField
Displays output from the following registers in
hexadecimal format:
• P_FEBE—Total number of Far End Block
Errors (FEBEs) that occurred on the path that
is associated with this interface.
• L_FE_BIP—Total number of far end BIP errors
that occurred on this interface.
• L_BIP—Total number of local BIP errors that
occurred on this interface.
• P_BEC—Total BIP error count (BEC) that
occurred on the path that is associated with this
interface.
• S_BIP—Total number of far end BIP errors that
occurred on the current section.
• J1-Rx0—Characters from far end IPV4 address
string.
• J1-Rx1—Characters from far end IPV4 address
string.
• J1-Rx2—Characters from far end IPV4 address
string.
• J1-Rx3—Characters from far end IPV4 address
string.
• J1-Rx4—Characters from far end IPV4 address
string.
• J1-Rx5—Characters from far end IPV4 address
string.
• J1-Rx6—Characters from far end IPV4 address
string.
• J1-Rx7—Characters from far end IPV4 address
string.
The following Serdes-WIS HW registers are used
to debug counters and can be cleared only by power
cycling the
hardware:P_FEBEL_FE_BIPL_BIPP_BECS_BIPThe
J1-Rx registers (J1-Rx0 through J1-Rx7) comprise
the raw 16 bytes of data received from the Rx J1
Path Trace Buffer, and are used to debug IPV4
address sent from far end.
Note
REGISTERS
Cisco ASR 9000 Series Aggregation Services Router Interface and Hardware Component Command Reference,
Release 5.3.x
1112
10-Gigabit Ethernet WAN PHY Controller Commandson the Cisco ASR 9000 Series Router
show controllers wanphy