Interrupt and trap functions UM0404
100/564 DocID13284 Rev 2
Reset conditions have priority over every other system activity and therefore have the
highest priority (trap priority III).
Software traps may be initiated to any vector location between 00’0000h and 00’01FCh. A
service routine entered via a software TRAP instruction is always executed on the current
CPU priority level which is indicated in bit-field ILVL in register PSW.
This means that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
5.1.1 Normal interrupt processing and PEC service
At each instruction cycle, among all the sources, which require a PEC or an interrupt
processing, only the one with the highest priority is selected. The priority of interrupts and
PEC requests is programmable in two levels. Each requesting source can be assigned to a
specific priority.
A second level (called “group priority”) allows to specify an internal order for simultaneous
requests from a group of different sources on the same priority level.
At the end of each instruction cycle the request with the highest current priority will be
determined by the interrupt system. The request will be serviced. If its priority is higher than
the current CPU priority which is stored in the register PSW.
5.1.2 Interrupt system register description
Interrupt processing is globally controlled by register PSW through a general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources
are individually controlled by their specific interrupt control registers (...IC).
Thus, the acceptance of requests by the CPU is determined by both the individual interrupt
control registers and the PSW. PEC services are controlled by the respective PECCx
register and the source and destination pointers, which specify the task of the respective
PEC service channel.
5.1.3 Interrupt control registers
All interrupt control registers are identically organized. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated source,
which is required during one round of prioritization, the upper 8 bits of the respective register
are reserved. All interrupt control registers are bit addressable and all bits can be read or
written via software.
This allows each interrupt source to be programmed or modified with just one instruction.
When accessing interrupt control registers through instructions which operate on word data
types, their upper 8 bits (15...8) will return zeros, when read, and will discard written data.
The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.
xxIC (yyyyh / zzh) SFR Reset Value: - - 00h
1514131211109876543210
--------xxIR xxIE ILVL GLVL
RW RW RW RW
To Next Page
Loading...
