DocID13284 Rev 2 111/564
UM0404 Interrupt and trap functions
In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags,
the interrupt response time may additionally be extended by two CPU clock cycles.
The worst case interrupt response time during internal Flash program execution adds to 12
CPU clock cycles.
Any reference to external locations increases the interrupt response time due to pipeline
related access priorities. The following conditions have to be considered:
• Instruction fetch from an external location
• Operand read from an external location
• Result write-back to an external location
Depending on where the instructions, source and destination operands are located, there is
a number of combinations. Note, however, that only access conflicts contribute to the delay.
The following is four examples to illustrate these delays:
• The worst case interrupt response time including external accesses, occurs when
instructions N, N+1 and N+2 are executed from external memory, instructions N-1 and
N require external operand read accesses, instructions N-3 to N write back external
operands, and the interrupt vector also points to an external location. In this case the
interrupt response time is the time to perform nine word bus accesses, because
instruction I1 cannot be fetched via the external bus until all write, fetch and read
requests of preceding instructions in the pipeline are terminated.
• When the above example has the interrupt vector pointing into the internal Flash, the
interrupt response time is 7 word bus accesses plus 2 CPU clock cycles, because
fetching of instruction I1 from internal Flash can start earlier.
• When instructions N, N+1 and N+2 are executed out of external memory and the
interrupt vector also points to an external location, but all operands for instructions N-3
through N are in internal memory, then the interrupt response time is the time to
perform three word bus accesses.
• When the above example has the interrupt vector pointing into the internal Flash, the
interrupt response time is one word bus access plus four CPU clock cycles.
After an interrupt service routine has been terminated by executing the RETI instruction,
and if further interrupts are pending, the next interrupt service routine will not be entered
until at least two instruction cycles have been executed of the program that was interrupted.
In most cases two instructions will be executed during this time. Only one instruction will
typically be executed if the first instruction following the RETI instruction is a branch
instruction (without cache hit), or if it reads an operand from internal Flash, or if it is
executed out of the IRAM.
Note: A bus access in this context also includes delays caused by an external READY
signal or by
bus arbitration (HOLD mode).
5.5.1 PEC response times
The PEC response time defines the time from an interrupt request flag of an enabled
interrupt source being set until the PEC data transfer being started. The basic PEC
response time for the ST10F276 is two instruction cycles.
To Next Page
Loading...
