The central processing unit (CPU) UM0404
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flag represents the logical NORing of the two specified bits. For the prioritize ALU operation
the Z-flag indicates, if the second operand was zero or not.
E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement
operations. The E-flag is cleared by those instructions which cannot be reasonably used for
table search operations. In all other cases the E-flag is set depending on the value of the
source operand to signify whether the end of a search table is reached or not.
If the value of the source operand of an instruction equals the lowest negative number,
which is representable by the data format of the corresponding instruction ('8000h' for the
word data type, or '80h' for the byte data type), the E-flag is set to '1', otherwise it is cleared.
MULIP-Flag: The MULIP-flag is set to '1' by hardware upon the entrance into an interrupt
service routine, when a multiply or divide ALU operation is interrupted before completion.
Depending on the state of the MULIP bit, the hardware decides whether a multiplication or
division must be continued or not after the end of an interrupt service. The MULIP bit is
overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt-
instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again
after that.
Note: The MULIP flag is a part of the task environment. When the interrupting service routine does
not return to the interrupted multiply/divide instruction (for example in case of a task
scheduler that switches between independent tasks), the MULIP flag must be saved as part
of the task environment and must be updated accordingly for the new task before this task is
entered.
CPU interrupt status (IEN, ILVL): The Interrupt Enable bit allows to globally enable
(IEN=’1’) or disable (IEN=’0’) interrupts. The 4-bit Interrupt Level field (ILVL) specifies the
priority of the current CPU activity.
The interrupt level is updated by hardware upon entry into an interrupt service routine, but it
can also be modified via software to prevent other interrupts from being acknowledged. In
case an interrupt level '15' has been assigned to the CPU, it has the highest possible
priority, and thus the current CPU operation cannot be interrupted except by hardware traps
or external non-maskable interrupts. For details refer to Section 5: Interrupt and trap
functions on page 96.
After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is assigned to
the initial CPU activity.
3.4.6 The instruction pointer IP
This register determines the 16-bit intra-segment address of the currently fetched instruction
within the code segment selected by the CSP register.
The IP register is not mapped into the MCU address space, and thus it is not directly
accessible by the programmer. The IP can, however, be modified indirectly via the stack by
means of a return instruction.
The IP register is implicitly updated by the CPU for branch instructions and after instruction
fetch operations.
IP (---- / --) --- Reset Value: 0000h
1514131211109876543210
IP
(R)(W)
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