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UM0404 XBUS asynchronous / synchronous serial interface
11 XBUS asynchronous / synchronous serial interface
A second Asynchronous/Synchronous Serial Interface (XASC) is implemented on
ST10F276. It is mapped on XBUS interface (Address range 00’E900h-00’E9FFh) and
provides serial communication between the ST10F276 and other microcontrollers,
microprocessors or external peripherals. The XASC is enabled by setting XPEN bit 2 of
SYSCON register and bit 7 of XPERCON register.
In synchronous mode, data are transmitted or received synchronously to a shift clock which
is generated by the ST10F276. In asynchronous mode, 8- or 9-bit data transfer, parity
generation, and the number of stop bits can be selected. Parity, framing, and overrun error
detection is provided to increase the reliability of data transfers. Transmission and reception
of data is double-buffered.
For multiprocessor communication, a mechanism to distinguish address from data byte is
included. Testing is supported by a loop-back option. A 13-bit Baud rate generator provides
the XASC with a separate serial clock signal.
The main differences between ASC0 and XASC are restricted to the programming model
and interrupt management, due to the constraints imposed by the XBUS with respect to the
standard ST10 peripheral bus (registers are not bit addressable, XBUS interrupt channels
sharing with other X-Peripherals). In terms of general functionality and performance, the two
modules are completely equivalent.
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