ST ST10F276E - Bit-Handling and Bit-Protection

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UM0404 The central processing unit (CPU)
Changing the system configuration
The instruction following an instruction that changes the system configuration via register
SYSCON (like the mapping of the internal memory, like segmentation, like stack size),
cannot use the new resources (Memory or stack). This instruction must not access the new
resources.
Code accesses to the new Memory area are only possible after an absolute branch to this
area. As a rule, instructions that change Memory mapping must be executed from IRAM or
external memory.
BUSCON/ADDRSEL
The (I
n+1
) instruction following an (I
n
) instruction that changes the properties of an external
address area, cannot access operands within the new area.
This instruction (I
n+1
) must not access this memory area. Code accesses to the new
address area must be made after an absolute branch to this area.
Note: As a rule, instructions that change external bus properties must not be executed from the
respective external memory area.
Timing
Pipeline architecture drastically reduces the average instruction processing time. The mean
ratio is about four to one instruction cycle. Some peculiar cases of pipeline configuration
extend the instruction processing time by half or by one cycle.
These cases have to be taken into account for the time critical software routines. Besides a
general execution time description, the following section provides some hints on how to
optimize time-critical program parts with regard to such pipeline-caused timing
particularities.
3.2 Bit-handling and bit-protection
The ST10F276 provides several mechanisms for bit manipulation. These mechanisms,
either handle software flags within the IRAM, control on-chip peripherals via control bits in
their respective SFRs, or control I/O functions via port pins.
The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV and BMOVN, explicitly set or
clear specific bits. The instructions BFLDL and BFLDH make it possible to change up to 8
bits of a specific byte at a time.
The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is
taken. The instructions JB and JNB (also conditional jump instructions that refer to flags)
evaluate the specified bit to determine if the jump is to be taken.
Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while the write
access will not affect the respective bit location.
NOP ; any instruction not accessing Port3
BSET P3.5 ; P3.13 is now output,
; the read-modify-write reads the P3.13 output
; latch