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UM0404 Analog / digital converter
at the end of the conversion (or sequence of conversions if Scan mode was selected), the
ADC is switched off (as soon as ADBSY bit is cleared).
When ADC is off (ADOFF bit set), setting bit ADST wakes automatically up the ADC and a
conversion starts: the accuracy is unfortunately not yet granted, since the analog circuitry
needs at least 50μs to complete the power-up transient phase. It is recommended to clear
ADOFF bit first, and only after 50μs to start the first conversion.
Note: If bit ADOFF is set and when ADST is set also, at the end of the conversion (or cycle of
conversion if Scan mode is selected), the ADC is switched off again (as soon as ADBSY is
cleared).
Turning off ADC consumption (setting bit ADOFF) should be done once the Calibration is
completed (starts after every reset occurrence): on the contrary, the calibration is stopped
by setting bit ADOFF, and not restarted/completed once bit ADOFF is cleared again.
19.2 Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
V
AREF
pin.
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the ST10F276 relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent of
the general speed of the controller. This allows adjusting the A/D converter of the ST10F276
to the properties of the system:
Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher
value, or the possible maximum.
This is preferable when using analog sources and supply with a high internal resistance in
order to keep the current as low as possible. The conversion rate in this case may be
considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where f
CPU
= 1/2TCL.
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