ST ST10F276E - I 2 C Interface; Main Features

I
2
C interface UM0404
392/564 DocID13284 Rev 2
20 I
2
C interface
The I
2
C is enabled by setting XPEN, bit 2 of the SYSCON register and bit XI2CEN of
XPERCON register. Once this is done, pins P4.4 and P4.7 becomes fully dedicated to I
2
C
interface and all the other alternate functions are bypassed (external memory and CAN2
functions). The pins are also automatically configured as Open-Drain as requested by the
I
2
C bus standard. The Port4 control registers P4, DP4 and ODP4 can no longer control P4.7
and P4.4 pin configuration: writing in the bits corresponding to P4.4 and P4.7 in these
registers has no effect on pins activity.
The I
2
C Bus Interface serves as an interface between the microcontroller and a serial I
2
C
bus. It provides both multi-master and slave functions, and controls all I
2
C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I
2
C mode (400 kHz).
20.1 Main features
• Parallel-bus/I
2
C protocol converter
• Multi-master capability
• 7-bit/10-bit addressing
• Transmitter/receiver flag
• End-of-byte transmission flag
• Transfer problem detection
• Standard/fast I
2
C mode
I
2
C timing diagram I
2
C master features:
• Clock generation
• I
2
C bus busy flag
• Arbitration lost flag
• End of byte transmission flag
• Transmitter/receiver flag
• Start bit detection flag
• Start and stop generation
I
2
C slave features:
• Stop bit detection
• I
2
C bus busy flag
• Detection of misplaced start or stop condition
• Programmable I
2
C address detection
• Transfer problem detection
• End-of-byte transmission flag
• Transmitter/receiver flag