Interrupt and trap functions UM0404
132/564 DocID13284 Rev 2
When an implicit decrement of the SP is made through a PUSH or CALL instruction, or upon
interrupt or trap entry, the IP value pushed is the address of the following instruction. When
the SP is decremented by a subtract instruction, the IP value pushed represents the
address of the instruction after the instruction following the subtract instruction.
For recovery from stack overflow it must be ensured that there is enough excess space on
the stack for saving the current system state (PSW, IP, in segmented mode also CSP) twice.
Otherwise, a system reset should be generated.
5.8.5 Stack underflow trap
Whenever the stack pointer is incremented to a value which is greater than the value in the
stack underflow register STKUN, the STKUF flag is set in register TFR and the CPU will
enter the stack underflow trap routine. Again, the IP value pushed onto the system stack
depends on which operation caused the increment of the SP. When an implicit increment of
the SP is made through a POP or return instruction, the IP value pushed is the address of
the following instruction.
When the SP is incremented by an add instruction, the pushed IP value represents the
address of the instruction after the instruction following the add instruction.
5.8.6 Undefined opcode trap
When the instruction currently decoded by the CPU does not contain a valid ST10F276
opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode
trap routine. The IP value pushed onto the system stack is the address of the instruction that
caused the trap.
This can be used to emulate non-implemented instructions. The trap service routine can
examine the faulting instruction to decode operands for non-implemented opcodes based
on the stacked IP. In order to resume processing, the stacked IP value must be incremented
by the size of the undefined instruction, which is determined by the user, before a RETI
instruction is executed.
5.8.7 MAC interrupt
The MAC can generate an interrupt according to the value of the status flags C (carry), SV
(overflow), E (extension) or SL (limit) of the MSW. The MAC interrupt is globally enabled
when the MIE flag in MCW is set. When it is enabled the flags C, SV, E or SL can trigger a
MAC interrupt when they are set, provided that the corresponding mask flag CM, VM, EM or
LM in MCV is also set. A MAC interrupt request sets the MIR flag in MSW: this flag must be
reset by the user during the interrupt routine, otherwise the interrupt processing restarts
when returning from the interrupt routine.
5.8.8 Protection fault trap
The format of the protected instructions is 4 byte wide. Byte 1 and 2 are complementary
values. Byte 3 and 4 are identical to byte 1. For example the format of SRST instruction is
B7h 48h B7h B7h. If the format of a protected instruction going to be executed does not
fulfill this coding, the PRTFLT flag in register TFR is set and the CPU enters the protection
fault trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN, SRST
and SRVWDT. When the protection fault trap occurs, the IP value pushed onto the system
stack is the address of the faulty instruction.
To Next Page
Loading...
