ST ST10F276E - Figure 198. Synchronous Long Hardware RESET (EA = 1)

System reset UM0404
482/564 DocID13284 Rev 2
Figure 198. Synchronous long hardware RESET (EA = 1)
P0[15:13] not transparent
RSTF
P0[12:2]
transparent
not t.
P0[1:0]
not t.
not transparent
FLARST
RST
≤ 1 ms
1024+8 TCL
≤ 2 TCL
1)
V
RPD
> 2.5V Asynchronous Reset not entered
200
μ A Discharge
RPD
RSTOUT
At this time RSTF is sampled LOW
so it is definitely LONG reset
(After Filter)
RSTIN
1024+8 TCL≤4 TCL
2)
≤12 TCL
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
IBUS-CS
7 TCL
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered. Even if RPD returns above the threshold,
2. Minimum RSTIN
low pulse duration should also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
not t.
transparent
not t.
3..4 TCL
(Internal)
the reset is defnitively taken as asynchronous.